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» Gate Sizing Using a Statistical Delay Model
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PATMOS
2007
Springer
14 years 3 months ago
A Statistical Approach to the Timing-Yield Optimization of Pipeline Circuits
Abstract. The continuous miniaturization of semiconductor devices imposes serious threats to design robustness against process variations and environmental fluctuations. Modern ci...
Chin-Hsiung Hsu, Szu-Jui Chou, Jie-Hong Roland Jia...
TON
2002
125views more  TON 2002»
13 years 8 months ago
Multicast-based inference of network-internal delay distributions
Packet delay greatly influences the overall performance of network applications. It is therefore important to identify causes and location of delay performance degradation within ...
Francesco Lo Presti, Nick G. Duffield, Joseph Horo...
ICISC
2008
103views Cryptology» more  ICISC 2008»
13 years 10 months ago
Generalized Universal Circuits for Secure Evaluation of Private Functions with Application to Data Classification
Secure Evaluation of Private Functions (PF-SFE) allows two parties to compute a private function which is known by one party only on private data of both. It is known that PF-SFE c...
Ahmad-Reza Sadeghi, Thomas Schneider 0003
ITC
1998
IEEE
120views Hardware» more  ITC 1998»
14 years 1 months ago
Test generation in VLSI circuits for crosstalk noise
This paper addresses the problem of efficiently and accurately generating two-vector tests for crosstalk induced effects, such as pulses, signal speedup and slowdown, in digital c...
Weiyu Chen, Sandeep K. Gupta, Melvin A. Breuer
DAC
2002
ACM
14 years 10 months ago
A physical model for the transient response of capacitively loaded distributed rlc interconnects
Rapid approximation of the transient response of high-speed global interconnects is needed to estimate the time delay, crosstalk, and overshoot in a GSI multilevel wiring network....
Raguraman Venkatesan, Jeffrey A. Davis, James D. M...