694 search results - page 60 / 139 » Gate Sizing Using a Statistical Delay Model |
MEMOCODE
2007
IEEE
14 years 3 months ago
2007
IEEE
—With the arrival of nanometer technologies wire delays are no longer negligible with respect to gate delays, and timing-closure becomes a major challenge to System-on-Chip desig...
DAC
2009
ACM
14 years 10 months ago
2009
ACM
Exponentially rising cooling/packaging costs due to high power density call for architectural and software-level thermal management. Dynamic thermal management (DTM) techniques co...
IJCNLP
2005
Springer
14 years 2 months ago
2005
Springer
The merit of phrase-based statistical machine translation is often reduced by the complexity to construct it. In this paper, we address some issues in phrase-based statistical mach...
ISQED
2009
IEEE
14 years 3 months ago
2009
IEEE
A system-level statistical analysis methodology is described that captures the impact of inter- and intra-die process variations for read timing failures in SRAM circuit blocks. U...
ICCCN
2007
IEEE
14 years 3 months ago
2007
IEEE
Abstract— Packet delay and bandwidth are two important metrics for measuring quality of service (QoS) of Internet services. Traditionally, packet delay differentiation and fair b...