694 search results - page 72 / 139 » Gate Sizing Using a Statistical Delay Model |
EACL
2003
ACL Anthology
13 years 11 months ago
2003
ACL Anthology
We present a neural-network-based statistical parser, trained and tested on the Penn Treebank. The neural network is used to estimate the parameters of a generative model of left-...
VLSID
2002
IEEE
14 years 10 months ago
2002
IEEE
The improved T and improved n models are proposed for onchip interconnect macromodeling. Using global approximations, simple approximation frames are derived and applied to modeli...
ISLPED
1999
ACM
14 years 2 months ago
1999
ACM
Abstract – In this paper, we propose a modeling approach for the average power consumption of macro-blocks that are typically used in digital signal processing (DSP) systems, suc...
ICCD
2008
IEEE
14 years 7 months ago
2008
IEEE
—Dynamic voltage scaling (DVS) provides power savings for systems with varying performance requirements. One low overhead implementation of DVS uses PMOS power switches to connec...
IPPS
1998
IEEE
14 years 2 months ago
1998
IEEE
This paper presents our work on the static task scheduling model using the mean-field annealing (MFA) technique. Mean-field annealing is a technique of thermostatic annealing that...