694 search results - page 78 / 139 » Gate Sizing Using a Statistical Delay Model |
BC
2004
13 years 10 months ago
2004
It is known that the springlike properties of muscles provide automatic load compensation during weight bearing. How crucial is sensory control of the motor output given these basi...
ISVLSI
2005
IEEE
14 years 3 months ago
2005
IEEE
— Direct tunneling current is the major component of static power dissipation of a CMOS circuit for technology below 65nm, where the gate dielectric (SiO2) is very low. We intuit...
DAC
2006
ACM
14 years 11 months ago
2006
ACM
As VLSI technology scales toward 65nm and beyond, both timing and power performance of integrated circuits are increasingly affected by process variations. In practice, people oft...
AIEDU
2006
13 years 10 months ago
2006
Constructing a student model for language tutors is a challenging task. This paper describes using knowledge tracing to construct a student model of reading proficiency and validat...
PATMOS
2005
Springer
14 years 3 months ago
2005
Springer
This paper presents a modular optimization framework for custom digital circuits in the power – performance space. The method uses a static timer and a nonlinear optimizer to max...