44 search results - page 4 / 9 » Gate delay calculation considering the crosstalk capacitance... |
PATMOS
2005
Springer
14 years 15 days ago
2005
Springer
The time taken for a CMOS logic gate output to change after one or more inputs have changed is called the output delay of the gate. A conventional multi-input CMOS gate is designed...
DAC
2000
ACM
14 years 8 months ago
2000
ACM
We revisit a basic element of modern signal integrity analysis, the modeling of worst-case coupling capacitance effects within a switch factor (SF) based methodology. We show that...
ISVLSI
2006
IEEE
14 years 1 months ago
2006
IEEE
— The effects of parameter variations and crosstalk noise on the clock signal propagating along an H-tree clock distribution network are investigated in this paper. In particular...
ICCD
2008
IEEE
14 years 4 months ago
2008
IEEE
—IR drop noise has become a critical issue in advanced process technologies. Traditionally, timing analysis in which the IR drop noise is considered assumes a worst-case IR drop ...
ISCAS
2006
IEEE
14 years 1 months ago
2006
IEEE
— With the transition to deep submicron technologies the density of on-chip interconnect lines has increased, together with the switching rate of the signals propagating along th...