7 search results - page 1 / 2 » Gate sizing by Lagrangian relaxation revisited |
ICCAD
2007
IEEE
14 years 7 months ago
2007
IEEE
ICCAD
1998
IEEE
14 years 3 months ago
1998
IEEE
This paper considers simultaneous gate and wire sizing for general very large scale integrated (VLSI) circuits under the Elmore delay model. We present a fast and exact algorithm w...
ICCAD
2002
IEEE
14 years 7 months ago
2002
IEEE
─ In this paper, we present Forge, an optimal algorithm for gate sizing using the Elmore delay model. The algorithm utilizes Lagrangian relaxation with a fast gradient-based pre-...
ICCAD
2004
IEEE
14 years 7 months ago
2004
IEEE
Abstract— This paper presents a post-route, timingconstrained gate-sizing algorithm for crosstalk reduction. Gate-sizing has emerged as a practical and feasible method to reduce ...
ICCAD
2006
IEEE
14 years 7 months ago
2006
IEEE
With the advent of deep sub-micron (DSM) era, floorplanning has become increasingly important in physical design process. In this paper we clarify a misunderstanding in using Lag...