36 search results - page 5 / 8 » Gate sizing for large cell-based designs |
DAC
2006
ACM
14 years 8 months ago
2006
ACM
Due to the shrinking of feature size and reduction in supply voltages, nanoscale circuits have become more susceptible to radiation induced transient faults. In this paper, we pre...
ASAP
2008
IEEE
14 years 2 months ago
2008
IEEE
Process technology has reduced in size such that it is possible to implement complete applicationspecific architectures as Systems-on-Chip (SoCs) using both Application-Specific I...
ISCAS
2006
IEEE
14 years 1 months ago
2006
IEEE
—This paper introduces a technique to measure and adjust the relative phase of on-chip high speed digital signals using a random sampling technique of inferential statistics. The...
ISQED
2003
IEEE
14 years 28 days ago
2003
IEEE
To save layout area for electrostatic discharge (ESD) protection design in the SOC era, test chip with large size NMOS devices placed under bond pads has been fabricated in 0.35-Â...
CARDIS
2006
Springer
13 years 11 months ago
2006
Springer
Most present symmetric encryption algorithms result from a tradeoff between implementation cost and resulting performances. In addition, they generally aim to be implemented effici...