28 search results - page 2 / 6 » Gate-level current waveform simulation of CMOS integrated ci... |
ISCAS
2007
IEEE
14 years 1 months ago
2007
IEEE
— Scaling of CMOS technologies has led to dramatic increase in sub-threshold, gate and reverse biased junction band-to-band-tunneling (BTBT) leakage. Leakage current has now beco...
MSE
1999
IEEE
13 years 11 months ago
1999
IEEE
This paper presents a PC based software running on PC dedicated to the training in sub-micron CMOS VLSI design. The software firstly consists in a HDL-based schematic editor with ...
TCAD
2010
13 years 5 months ago
2010
—With the scaling of complementary metal–oxide– semiconductor (CMOS) technology into the nanometer regime, the overshooting effect due to the input-to-output coupling capacit...
SBCCI
2004
ACM
14 years 16 days ago
2004
ACM
This paper presents a design methodology for RF CMOS Low Noise Amplifiers (LNA). This methodology uses a current–based MOSFET model, which allows a detailed analysis of an LNA f...
SBCCI
2004
ACM
14 years 16 days ago
2004
ACM
This paper presents an approach for simulation of mixed analog-digital CMOS integrated circuits, aiming at estimating crosstalk effects due to current pulses drawn from voltage s...