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» Gathering Algorithms on Paths Under Interference Constraints
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SASP
2008
IEEE
101views Hardware» more  SASP 2008»
14 years 2 months ago
Custom Processor Core Construction from C Code
—In this paper we present a method for construction of application specific processor cores from a given C code. Our approach consists of three phases. We start by quantifying t...
Jelena Trajkovic, Daniel D. Gajski
ICCAD
2004
IEEE
158views Hardware» more  ICCAD 2004»
14 years 4 months ago
DAOmap: a depth-optimal area optimization mapping algorithm for FPGA designs
In this paper we study the technology mapping problem for FPGA architectures to minimize chip area, or the total number of lookup tables (LUTs) of the mapped design, under the chi...
Deming Chen, Jason Cong
ICCAD
2008
IEEE
140views Hardware» more  ICCAD 2008»
14 years 4 months ago
Algorithms for simultaneous consideration of multiple physical synthesis transforms for timing closure
We propose a post-placement physical synthesis algorithm that can apply multiple circuit synthesis and placement transforms on a placed circuit to improve the critical path delay ...
Huan Ren, Shantanu Dutt
ICIP
2007
IEEE
14 years 9 months ago
Lifetime-Distortion Trade-off in Image Sensor Networks
We examine the trade-off between lifetime and distortion in image sensor networks deployed for gathering visual information over a monitored region. Users navigate over the monito...
Chao Yu, Stanislava Soro, Gaurav Sharma, Wendi Rab...
FPL
2005
Springer
112views Hardware» more  FPL 2005»
14 years 1 months ago
Hierarchical Placement for Large-scale FPAA
Abstract— Modern advances in reconfigurable analog technologies are allowing field-programmable analog arrays (FPAAs) to dramatically grow in size, flexibility, and usefulness...
I. Faik Baskaya, Sasank Reddy, Sung Kyu Lim, David...