268 search results - page 13 / 54 » Gating currents |
ISCAS
2007
IEEE
14 years 1 months ago
2007
IEEE
TheRFdesignparadigm will changesignificantly asCMOS technology scales and integration levels rise to accommodate multi-band, multi-mode transceivers and baseband processors. This...
CHES
2005
Springer
14 years 1 months ago
2005
Springer
Abstract. It has recently been shown that logic circuits in the implementation of cryptographic algorithms, although protected by “secure” random masking schemes, leak side-cha...
ASPDAC
2006
ACM
14 years 1 months ago
2006
ACM
— Sakurai-Newton (SN) delay metric [1] is a widely used closed form delay metric for CMOS gates because of simplicity and reasonable accuracy. Nevertheless it can be shown that t...
TCAD
2008
13 years 7 months ago
2008
Abstract--Design of a suitable power gating (e.g., multithreshold CMOS or super cutoff CMOS) structure is an important and challenging task in sub-90nm VLSI circuits where leakage ...
ISLPED
2004
ACM
14 years 27 days ago
2004
ACM
Leakage power is a major concern in current and future microprocessor designs. In this paper, we explore the potential of architectural techniques to reduce leakage through power-...