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DAC
2004
ACM
14 years 8 months ago
Worst-case circuit delay taking into account power supply variations
Current Static Timing Analysis (STA) techniques allow one to verify the timing of a circuit at different process corners which only consider cases where all the supplies are low o...
Dionysios Kouroussis, Rubil Ahmadi, Farid N. Najm
DAC
2004
ACM
13 years 11 months ago
Leakage in nano-scale technologies: mechanisms, impact and design considerations
The high leakage current in nano-meter regimes is becoming a significant portion of power dissipation in CMOS circuits as threshold voltage, channel length, and gate oxide thickne...
Amit Agarwal, Chris H. Kim, Saibal Mukhopadhyay, K...
VLSID
2005
IEEE
149views VLSI» more  VLSID 2005»
14 years 8 months ago
ADOPT: An Approach to Activity Based Delay Optimization
: The direct result of shrinking devices is not only higher densities but also increased switching activity and thus higher device temperatures. The variation in temperature over t...
Gaurav Arora, Abhishek Sharma, D. Nagchoudhuri, M....
VLSID
2005
IEEE
129views VLSI» more  VLSID 2005»
14 years 8 months ago
A RISC Hardware Platform for Low Power Java
Java is increasingly being used as a language and binary format for low power, embedded systems. Current software only approaches to Java execution do not always suit the type of ...
Paul Capewell, Ian Watson
ICCAD
2001
IEEE
108views Hardware» more  ICCAD 2001»
14 years 4 months ago
Multigrid-Like Technique for Power Grid Analysis
— Modern sub-micron VLSI designs include huge power grids that are required to distribute large amounts of current, at increasingly lower voltages. The resulting voltage drop on ...
Joseph N. Kozhaya, Sani R. Nassif, Farid N. Najm