268 search results - page 6 / 54 » Gating currents |
SBCCI
2004
ACM
14 years 27 days ago
2004
ACM
This paper presents a design methodology for RF CMOS Low Noise Amplifiers (LNA). This methodology uses a current–based MOSFET model, which allows a detailed analysis of an LNA f...
DATE
2006
IEEE
14 years 1 months ago
2006
IEEE
For CMOS technologies below 65nm, gate oxide direct tunneling current is a major component of the total power dissipation. This paper presents a simulated annealing based algorith...
ASPDAC
2009
ACM
14 years 2 months ago
2009
ACM
- The power gating technique is useful in reducing standby leakage current, but it increases the gate delay. For a functional unit, its maximum allowable delay (for a target clock ...
CTRSA
2005
Springer
14 years 1 months ago
2005
Springer
There are many articles and patents on the masking of logic gates. However, the existing publications assume that a masked logic gate switches its output no more than once per cloc...
ICCAD
2007
IEEE
14 years 4 months ago
2007
IEEE
- Power gating is an efficient technique for reducing leakage power in electronic devices by disconnecting blocks idle for long periods of time from the power supply. Disconnecting...