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ISVLSI
2007
IEEE
151views VLSI» more  ISVLSI 2007»
14 years 1 months ago
Design of a MCML Gate Library Applying Multiobjective Optimization
In this paper, the problem of sizing MOS Current Mode Logic (MCML) circuits is addressed. The Pareto front is introduced as a useful analysis tool to explore the design space of e...
Roberto Pereira-Arroyo, Pablo Alvarado-Moya, Wolfg...
PATMOS
2004
Springer
14 years 25 days ago
Signal Sampling Based Transition Modeling for Digital Gates Characterization
Current characterization methods introduce an important error in the measurement process. In this paper, we present a novel method to drive the timing characterization of logic gat...
Alejandro Millán, Jorge Juan-Chico, Manuel ...
DAC
2006
ACM
14 years 8 months ago
Gate sizing: finFETs vs 32nm bulk MOSFETs
FinFET devices promise to replace traditional MOSFETs because of superior ability in controlling leakage and minimizing short channel effects while delivering a strong drive curre...
Brian Swahn, Soha Hassoun
DAC
2006
ACM
14 years 8 months ago
Timing driven power gating
Power Gating is effective for reducing leakage power. Previously, a Distributed Sleep Transistor Network (DSTN) was proposed to reduce the sleep transistor area by connecting all ...
De-Shiuan Chiou, Shih-Hsin Chen, Shih-Chieh Chang,...
GLVLSI
2007
IEEE
114views VLSI» more  GLVLSI 2007»
14 years 1 months ago
Design of mixed gates for leakage reduction
Leakage power dissipation is one of the most critical factors for the overall current dissipation and future designs. However, design techniques for the reduction of leakage power...
Frank Sill, Jiaxi You, Dirk Timmermann