Sciweavers

3119 search results - page 575 / 624
» General Default Logic
Sort
View
ICCD
2008
IEEE
192views Hardware» more  ICCD 2008»
14 years 7 months ago
Energy-aware opcode design
— Embedded processors are required to achieve high performance while running on batteries. Thus, they must exploit all the possible means available to reduce energy consumption w...
Balaji V. Iyer, Jason A. Poovey, Thomas M. Conte
ICCAD
2006
IEEE
127views Hardware» more  ICCAD 2006»
14 years 7 months ago
Joint design-time and post-silicon minimization of parametric yield loss using adjustable robust optimization
Parametric yield loss due to variability can be effectively reduced by both design-time optimization strategies and by adjusting circuit parameters to the realizations of variable...
Murari Mani, Ashish Kumar Singh, Michael Orshansky
ICCAD
2003
IEEE
148views Hardware» more  ICCAD 2003»
14 years 7 months ago
The Compositional Far Side of Image Computation
Symbolic image computation is the most fundamental computation in BDD-based sequential system optimization and formal verification. In this paper, we explore the use of over-appr...
Chao Wang, Gary D. Hachtel, Fabio Somenzi
SOSP
2005
ACM
14 years 7 months ago
Implementing declarative overlays
Overlay networks are used today in a variety of distributed systems ranging from file-sharing and storage systems to communication infrastructures. However, designing, building a...
Boon Thau Loo, Tyson Condie, Joseph M. Hellerstein...
FPGA
2010
ACM
209views FPGA» more  FPGA 2010»
14 years 7 months ago
FPGA power reduction by guarded evaluation
Guarded evaluation is a power reduction technique that involves identifying sub-circuits (within a larger circuit) whose inputs can be held constant (guarded) at specific times d...
Chirag Ravishankar, Jason Helge Anderson