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HICSS
1995
IEEE
128views Biometrics» more  HICSS 1995»
13 years 11 months ago
Instruction Level Parallelism
Abstract. We reexamine the limits of parallelism available in programs, using runtime reconstruction of program data-flow graphs. While limits of parallelism have been examined in...
ICPPW
2007
IEEE
14 years 1 months ago
A Quality-Driven Algorithm for Resource Scheduling Based on Market Model on Grid
Several challenges about computational grid exist in integrating, coordinating and managing of resources and scheduling of applications, due to distributed resources at various le...
Lei Tang, Zhiyi Yang, Zhiwen Yu, Yunlan Wang
MICRO
1999
IEEE
110views Hardware» more  MICRO 1999»
13 years 11 months ago
Balance Scheduling: Weighting Branch Tradeoffs in Superblocks
Since there is generally insufficient instruction level parallelism within a single basic block, higher performance is achieved by speculatively scheduling operations in superbloc...
Alexandre E. Eichenberger, Waleed Meleis
DAC
2002
ACM
14 years 8 months ago
Energy estimation and optimization of embedded VLIW processors based on instruction clustering
Aim of this paper is to propose a methodology for the definition of an instruction-level energy estimation framework for VLIW (Very Long Instruction Word) processors. The power mo...
Andrea Bona, Mariagiovanna Sami, Donatella Sciuto,...
HPCA
1995
IEEE
13 years 11 months ago
The Effects of STEF in Finely Parallel Multithreaded Processors
The throughput of a multiple-pipelined processor suffers due to lack of sufficient instructions to make multiple pipelines busy and due to delays associated with pipeline depende...
Yamin Li, Wanming Chu