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ERSA
2009
129views Hardware» more  ERSA 2009»
13 years 5 months ago
Data path Configuration Time Reduction for Run-time Reconfigurable Systems
- The FPGA (re)configuration is a time-consuming process and a bottleneck in FPGA-based Run-Time Reconfigurable (RTR) systems. In this paper, we present a High Level Synthesis (HLS...
Mahmood Fazlali, Ali Zakerolhosseini, Mojtaba Sabe...
TCSV
2008
277views more  TCSV 2008»
13 years 7 months ago
Automatic Single View-Based 3-D Face Synthesis for Unsupervised Multimedia Applications
Abstract--Various 3-D face synthesis techniques have been proposed and extensively used in many applications. Compared with others, single view-based face synthesis technology allo...
Yun Sheng, Abdul H. Sadka, Ahmet M. Kondoz

Publication
303views
12 years 5 months ago
Evolutionary synthesis of analog networks
he significant increase in the available computational power that took place in recent decades has been accompanied by a growing interest in the application of the evolutionary ap...
Claudio Mattiussi
CODES
2007
IEEE
14 years 1 months ago
Simultaneous synthesis of buses, data mapping and memory allocation for MPSoC
Heterogeneous multiprocessors are emerging as the dominant implementation approach to embedded multiprocessor systems. In addition to having processing elements suited to the targ...
Brett H. Meyer, Donald E. Thomas
CODES
2006
IEEE
14 years 1 months ago
Data reuse driven energy-aware MPSoC co-synthesis of memory and communication architecture for streaming applications
The memory subsystem of a complex multiprocessor systemson-chip (MPSoC) is an important contributor to the chip power consumption. The selection of memory architecture, as well as...
Ilya Issenin, Nikil Dutt