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TC
2010
13 years 8 months ago
Design and Analysis of On-Chip Networks for Large-Scale Cache Systems
—Switched networks have been adopted in on-chip communication for their scalability and efficient resource sharing. However, using a general network for a specific domain may res...
Yuho Jin, Eun Jung Kim, Ki Hwan Yum
TVLSI
2010
13 years 4 months ago
C-Pack: A High-Performance Microprocessor Cache Compression Algorithm
Microprocessor designers have been torn between tight constraints on the amount of on-chip cache memory and the high latency of off-chip memory, such as dynamic random access memor...
Xi Chen, Lei Yang, Robert P. Dick, Li Shang, Haris...
SIGMETRICS
2011
ACM
178views Hardware» more  SIGMETRICS 2011»
13 years 25 days ago
Soft error benchmarking of L2 caches with PARMA
The amount of charge stored in an SRAM cell shrinks rapidly with each technology generation thus increasingly exposing caches to soft errors. Benchmarking the FIT rate of caches d...
Jinho Suh, Mehrtash Manoochehri, Murali Annavaram,...
ICPADS
2007
IEEE
14 years 4 months ago
Persistence and communication state transfer in an asynchronous pipe mechanism
Abstract— Emergent wide-area distributed systems like computational grids present opportunities for large scientific applications. On these systems, communication mechanisms hav...
Philip Chan, David Abramson
WWW
2002
ACM
14 years 10 months ago
Aliasing on the world wide web: prevalence and performance implications
Aliasing occurs in Web transactions when requests containing different URLs elicit replies containing identical data payloads. Conventional caches associate stored data with URLs ...
Terence Kelly, Jeffrey C. Mogul