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GLVLSI
2008
IEEE
140views VLSI» more  GLVLSI 2008»
14 years 3 months ago
A table-based method for single-pass cache optimization
Due to the large contribution of the memory subsystem to total system power, the memory subsystem is highly amenable to customization for reduced power/energy and/or improved perf...
Pablo Viana, Ann Gordon-Ross, Edna Barros, Frank V...
RTCSA
2008
IEEE
14 years 3 months ago
Impact of Cache Partitioning on Multi-tasking Real Time Embedded Systems
Cache partitioning techniques have been proposed in the past as a solution for the cache interference problem. Due to qualitative differences with general purpose platforms, real-...
Bach Duy Bui, Marco Caccamo, Lui Sha, Joseph Marti...
WWW
2005
ACM
14 years 9 months ago
Three-level caching for efficient query processing in large Web search engines
Large web search engines have to answer thousands of queries per second with interactive response times. Due to the sizes of the data sets involved, often in the range of multiple...
Xiaohui Long, Torsten Suel
ISCA
2009
IEEE
146views Hardware» more  ISCA 2009»
14 years 3 months ago
Multi-execution: multicore caching for data-similar executions
While microprocessor designers turn to multicore architectures to sustain performance expectations, the dramatic increase in parallelism of such architectures will put substantial...
Susmit Biswas, Diana Franklin, Alan Savage, Ryan D...
ASPLOS
2006
ACM
14 years 2 months ago
Software-based instruction caching for embedded processors
While hardware instruction caches are present in virtually all general-purpose and high-performance microprocessors today, many embedded processors use SRAM or scratchpad memories...
Jason E. Miller, Anant Agarwal