In a constraint-drivenlayout synthesisenvironment,parasitic constraints are generated and implemented in each phase of the design process to meet a given set of performance specif...
Edoardo Charbon, Paolo Miliozzi, Enrico Malavasi, ...
In this paper an extension of the IFAD VDM-SL Toolbox with a proof obligation generator is described. Static type checking in VDM is undecidable in general and therefore the type c...
Existing built-in self test (BIST) strategies require the use of specialized test pattern generation hardware which introduces signicant area overhead and performance degradation...
Functional verification is widely acknowledged as a major bottleneck in microprocessor design. While early work on specification driven functional test program generation has prop...
Simulations often depend heavily on random numbers, yet the impact of random number generators is recognized seldom. The generation of random numbers for simulations is not trivia...
Roland Ewald, Johannes Rossel, Jan Himmelspach, Ad...