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» Generating high performance pruned FFT implementations
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ISPD
2006
ACM
90views Hardware» more  ISPD 2006»
14 years 1 months ago
Fast buffer insertion considering process variations
Advanced process technologies call for a proactive consideration of process variations in design to ensure high parametric timing yield. Despite of its popular use in almost any h...
Jinjun Xiong, Lei He
VLSISP
2008
118views more  VLSISP 2008»
13 years 7 months ago
Analysis of Lifting and B-Spline DWT Implementations for Implantable Neuroprosthetics
Abstract. The large amount of data generated by neuroprosthetic devices requires a high communication bandwidth for extra-cranial transmission, critically limiting the number and u...
Awais M. Kamboh, Andrew Mason, Karim G. Oweiss
DATE
2009
IEEE
120views Hardware» more  DATE 2009»
14 years 2 months ago
Optimizing data flow graphs to minimize hardware implementation
Abstract - This paper describes an efficient graphbased method to optimize data-flow expressions for best hardware implementation. The method is based on factorization, common su...
Daniel Gomez-Prado, Q. Ren, Maciej J. Ciesielski, ...
ASPDAC
2007
ACM
156views Hardware» more  ASPDAC 2007»
13 years 11 months ago
Implementation of a Real Time Programmable Encoder for Low Density Parity Check Code on a Reconfigurable Instruction Cell Archit
- This paper presents a real time programmable irregular Low Density Parity Check (LDPC) Encoder as specified in the IEEE P802.16E/D7 standard. The encoder is programmable for fram...
Zahid Khan, Tughrul Arslan
ICS
2009
Tsinghua U.
14 years 2 months ago
Computer generation of fast fourier transforms for the cell broadband engine
The Cell BE is a multicore processor with eight vector accelerators (called SPEs) that implement explicit cache management through direct memory access engines. While the Cell has...
Srinivas Chellappa, Franz Franchetti, Markus P&uum...