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ECOOPW
1998
Springer
13 years 11 months ago
A Rational Approach to Portable High Performance: The Basic Linear Algebra Instruction Set (BLAIS) and the Fixed Algorithm Size
Abstract. We introduce a collection of high performance kernels for basic linear algebra. The kernels encapsulate small xed size computations in order to provide building blocks fo...
Jeremy G. Siek, Andrew Lumsdaine
DATE
2000
IEEE
97views Hardware» more  DATE 2000»
13 years 12 months ago
Layout-Oriented Synthesis of High Performance Analog Circuits
This paper presents a methodology towards synthesis of high performance analog circuits. Layout parasitics are estimated and compensated during circuit sizing. Physical layout con...
Mohamed Dessouky, Marie-Minerve Louërat, Jack...
HOTI
2008
IEEE
14 years 1 months ago
QsNetIII an Adaptively Routed Network for High Performance Computing
—In this paper we describe QsNetIII , an adaptively routed network for High Performance Computing (HPC) applications. We detail the structure of the network, the evolution of our...
Duncan Roweth, Trevor Jones
PPL
2008
185views more  PPL 2008»
13 years 7 months ago
On Design and Application Mapping of a Network-on-Chip(NoC) Architecture
As the number of integrated IP cores in the current System-on-Chips (SoCs) keeps increasing, communication requirements among cores can not be sufficiently satisfied using either ...
Jun Ho Bahn, Seung Eun Lee, Yoon Seok Yang, Jungso...
SAC
2006
ACM
14 years 1 months ago
Implementing an embedded GPU language by combining translation and generation
Dynamic languages typically allow programs to be written y high level of abstraction. But their dynamic nature makes it very hard to compile such languages, meaning that a price h...
Calle Lejdfors, Lennart Ohlsson