Layout-Oriented Synthesis of High Performance Analog Circuits

This paper presents a methodology towards synthesis of high performance analog circuits. Layout parasitics are estimated and compensated during circuit sizing. Physical layout constraints are thus taken into consideration early in the design. This approach shortens the overall design time by avoiding laborious sizing-layout iterations. The approach has been implemented using two knowledge-based tools dedicated to analog circuit sizing and layout generation. An example of a high performance OTA is presented at the end to illustrate the effectiveness of the approach.

• Type: Conference
• Year: 2000
• Where: DATE
• Authors: Mohamed Dessouky, Marie-Minerve Louërat, Jacky Porte
• Keywords: Analog Circuit, DATE 2000, Hardware, Laborious Sizing-layout Iterations, Physical Layout Constraints