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» Generation of BDDs from hardware algorithm descriptions
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IWSOC
2005
IEEE
112views Hardware» more  IWSOC 2005»
14 years 1 months ago
Practical Techniques for Performance Estimation of Processors
Performance estimation of processor is important to select the right processor for an application. Poorly chosen processors can either under perform very badly or over perform but...
Abhijit Ray, Thambipillai Srikanthan, Wu Jigang
DATE
2010
IEEE
153views Hardware» more  DATE 2010»
14 years 1 months ago
Recursion-driven parallel code generation for multi-core platforms
—We present Huckleberry, a tool for automatically generating parallel implementations for multi-core platforms from sequential recursive divide-and-conquer programs. The recursiv...
Rebecca L. Collins, Bharadwaj Vellore, Luca P. Car...
DIAL
2004
IEEE
164views Image Analysis» more  DIAL 2004»
13 years 11 months ago
A Dynamic Feature Generation System for Automated Metadata Extraction in Preservation of Digital Materials
Obsolescence in storage media and the hardware and software for access and use can render old electronic files inaccessible and unusable. Therefore, the long-term preservation of ...
Song Mao, Jongwoo Kim, George R. Thoma
VLSID
2004
IEEE
292views VLSI» more  VLSID 2004»
14 years 8 months ago
NoCGEN: A Template Based Reuse Methodology for Networks on Chip Architecture
In this paper, we describe NoCGEN, a Network On Chip (NoC) generator, which is used to create a simulatable and synthesizable NoC description. NoCGEN uses a set of modularised rou...
Jeremy Chan, Sri Parameswaran
CPE
1994
Springer
170views Hardware» more  CPE 1994»
13 years 12 months ago
Automatic Scalability Analysis of Parallel Programs Based on Modeling Techniques
When implementingparallel programs forparallel computer systems the performancescalability of these programs should be tested and analyzed on different computer configurations and...
Allen D. Malony, Vassilis Mertsiotakis, Andreas Qu...