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» Generation of BDDs from hardware algorithm descriptions
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ISQED
2000
IEEE
136views Hardware» more  ISQED 2000»
14 years 12 days ago
A Layout Approach for Electrical and Physical Design Integration of High-Performance Analog Circuits
This paper presents a layout generation tool that aims to reduce the gap between electrical sizing and physical realization of high performance analog circuits. The procedural lay...
Mohamed Dessouky, Marie-Minerve Louërat
ICCAD
1996
IEEE
112views Hardware» more  ICCAD 1996»
14 years 5 days ago
GRASP - a new search algorithm for satisfiability
This paper introduces GRASP (Generic seaRch Algorithm for the Satisfiability Problem), an integrated algorithmic framework for SAT that unifies several previously proposed searchp...
João P. Marques Silva, Karem A. Sakallah
ATS
1998
IEEE
170views Hardware» more  ATS 1998»
14 years 8 days ago
A Ring Architecture Strategy for BIST Test Pattern Generation
This paper presents a new effective Built-In Self Test (BIST) scheme that achieves 100% fault coverage with low area overhead, and without any modification of the circuit under tes...
Christophe Fagot, Olivier Gascuel, Patrick Girard,...
AAMAS
2008
Springer
13 years 8 months ago
DARE: a system for distributed abductive reasoning
Abductive reasoning is a well established field of Artificial Intelligence widely applied to different problem domains not least cognitive robotics and planning. It has been used ...
Jiefei Ma, Alessandra Russo, Krysia Broda, Keith C...
ICCD
2008
IEEE
151views Hardware» more  ICCD 2008»
14 years 5 months ago
Digital filter synthesis considering multiple adder graphs for a coefficient
—In this paper, a new FIR digital filter synthesis algorithm is proposed to consider multiple adder graphs for a coefficient. The proposed algorithm selects an adder graph that c...
Jeong-Ho Han, In-Cheol Park