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» Generation of compact test sets with high defect coverage
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ICCAD
2009
IEEE
101views Hardware» more  ICCAD 2009»
13 years 5 months ago
Compacting test vector sets via strategic use of implications
As the complexity of integrated circuits has increased, so has the need for improving testing efficiency. Unfortunately, the types of defects are also becoming more complex, which...
Nuno Alves, Jennifer Dworak, R. Iris Bahar, Kundan...
ATS
2009
IEEE
138views Hardware» more  ATS 2009»
14 years 2 months ago
Test Pattern Selection for Potentially Harmful Open Defects in Power Distribution Networks
Power distribution network (PDN) designs for today’s high performance integrated circuits (ICs) typically occupy a significant share of metal resources in the circuit, and henc...
Yubin Zhang, Lin Huang, Feng Yuan, Qiang Xu
DATE
2000
IEEE
121views Hardware» more  DATE 2000»
13 years 12 months ago
Functional Test Generation for Full Scan Circuits
We study the effectiveness of functional tests for full scan circuits. Functional tests are important for design validation, and they potentially have a high defect coverage indep...
Irith Pomeranz, Sudhakar M. Reddy
ATS
2009
IEEE
117views Hardware» more  ATS 2009»
14 years 2 months ago
N-distinguishing Tests for Enhanced Defect Diagnosis
Diagnostic ATPG has traditionally been used to generate test patterns that distinguish pairs of modeled faults. In this work, we investigate the use of n-distinguishing test sets,...
Gang Chen, Janusz Rajski, Sudhakar M. Reddy, Irith...
ATS
2005
IEEE
100views Hardware» more  ATS 2005»
14 years 1 months ago
Finite State Machine Synthesis for At-Speed Oscillation Testability
In this paper, we propose an oscillation-based test methodology for sequential testing. This approach provides many advantages over traditional methods. (1) It is at-speed testing...
Katherine Shu-Min Li, Chung-Len Lee, Tagin Jiang, ...