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CASES
2007
ACM
14 years 25 days ago
INTACTE: an interconnect area, delay, and energy estimation tool for microarchitectural explorations
Prior work on modeling interconnects has focused on optimizing the wire and repeater design for trading off energy and delay, and is largely based on low level circuit parameters....
Rahul Nagpal, Arvind Madan, Bharadwaj Amrutur, Y. ...
CASES
2006
ACM
14 years 17 days ago
Efficient architectures through application clustering and architectural heterogeneity
Customizing architectures for particular applications is a promising approach to yield highly energy-efficient designs for embedded systems. This work explores the benefits of arc...
Lukasz Strozek, David Brooks
DATE
2008
IEEE
145views Hardware» more  DATE 2008»
14 years 3 months ago
Minimizing Virtual Channel Buffer for Routers in On-chip Communication Architectures
We present a novel methodology for design space exploration using a two-steps scheme to optimize the number of virtual channel buffers (buffers take the premier share of the route...
Mohammad Abdullah Al Faruque, Jörg Henkel
JPDC
2008
147views more  JPDC 2008»
13 years 8 months ago
A Grid-based Virtual Reactor: Parallel performance and adaptive load balancing
This paper addresses the problem of porting distributed parallel applications to the Grid. One of the challenges we address is the change from static homogeneous cluster environmen...
Vladimir Korkhov, Valeria V. Krzhizhanovskaya, Pet...
DATE
2003
IEEE
86views Hardware» more  DATE 2003»
14 years 2 months ago
Layered, Multi-Threaded, High-Level Performance Design
A primary goal of high-level modeling is to efficiently explore a broad design space, converging on an optimal or near-optimal system architecture before moving to a more detaile...
Andrew S. Cassidy, JoAnn M. Paul, Donald E. Thomas