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VLSID
2004
IEEE
119views VLSI» more  VLSID 2004»
14 years 9 months ago
Rapid Prototyping for Configurable System-on-a-Chip Platforms: A Simulation Based Approach
The design of any application on a configurable System-on-a-Chip (SoC) like Atmel's FPSLIC is subject to a lot of constraints stemming from requirements of the application an...
Jens Bieger, Sorin A. Huss, Michael Jung, Stephan ...
INTEGRATION
2007
98views more  INTEGRATION 2007»
13 years 8 months ago
Hashchip: A shared-resource multi-hash function processor architecture on FPGA
The ubiquitous presence of mobile devices and the demand for better performance and efficiency have motivated research into embedded implementations of cryptography algorithms. I...
T. S. Ganesh, Michael T. Frederick, T. S. B. Sudar...
ISESE
2005
IEEE
14 years 2 months ago
Contextual reusability metrics for event-based architectures
Component Based Software Engineering has been perceived to have immense reuse potential. This area has evoked wide interest and has led to considerable investment in research and ...
Sutirtha Bhattacharya, Dewayne E. Perry
VLSID
2008
IEEE
150views VLSI» more  VLSID 2008»
14 years 9 months ago
PTSMT: A Tool for Cross-Level Power, Performance, and Thermal Exploration of SMT Processors
Simultaneous Multi-Threading (SMT) processors are becoming popular because they exploit both instruction-level and threadlevel parallelism by issuing instructions from different t...
Deepa Kannan, Aseem Gupta, Aviral Shrivastava, Nik...
DATE
2003
IEEE
151views Hardware» more  DATE 2003»
14 years 2 months ago
SPIN: A Scalable, Packet Switched, On-Chip Micro-Network
This paper presents the SPIN micro-network that is a generic, scalable interconnect architecture for system on chip. The SPIN architecture relies on packet switching and point-to-...
Adrijean Andriahantenaina, Hervé Charlery, ...