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ASPDAC
2005
ACM
90views Hardware» more  ASPDAC 2005»
13 years 10 months ago
An integrated performance and power model for superscalar processor designs
— On current superscalar processors, performance and power issues cannot be decoupled for designers. Extensive simulations are usually required to meet both power and performance...
Yongxin Zhu, Weng-Fai Wong, Stefan Andrei
IJNSEC
2008
106views more  IJNSEC 2008»
13 years 8 months ago
Parallel Hardware Architectures for the Cryptographic Tate Pairing
Identity-based cryptography uses pairing functions,which are sophisticated bilinear maps defined on elliptic curves.Computing pairings efficiently in software is presently a relev...
Guido Marco Bertoni, Luca Breveglieri, Pasqualina ...
ICASSP
2008
IEEE
14 years 3 months ago
Automatic synthesis of VLSI architectures for arbitrary lifting-based filter banks and transforms
Recently, the conventional lifting scheme that is widely used for the construction of Wavelets and 2-channel filter banks has been extended to M-channel filter banks (M > 2)....
Ruben Bartholomä, Thomas Greiner, Frank Kesel...
ISCA
2008
IEEE
188views Hardware» more  ISCA 2008»
14 years 3 months ago
MIRA: A Multi-layered On-Chip Interconnect Router Architecture
Recently, Network-on-Chip (NoC) architectures have gained popularity to address the interconnect delay problem for designing CMP / multi-core / SoC systems in deep sub-micron tech...
Dongkook Park, Soumya Eachempati, Reetuparna Das, ...
CASES
2004
ACM
14 years 2 months ago
Balancing design options with Sherpa
Application specific processors offer the potential of rapidly designed logic specifically constructed to meet the performance and area demands of the task at hand. Recently, t...
Timothy Sherwood, Mark Oskin, Brad Calder