Sciweavers

494 search results - page 85 / 99
» Generic Design Space Exploration for Reconfigurable Architec...
Sort
View
ISLPED
2005
ACM
108views Hardware» more  ISLPED 2005»
14 years 1 months ago
Replacing global wires with an on-chip network: a power analysis
This paper explores the power implications of replacing global chip wires with an on-chip network. We optimize network links by varying repeater spacing, link pipelining, and volt...
Seongmoo Heo, Krste Asanovic
IJHPCA
2010
117views more  IJHPCA 2010»
13 years 6 months ago
Fine-Grained Multithreading Support for Hybrid Threaded MPI Programming
As high-end computing systems continue to grow in scale, recent advances in multiand many-core architectures have pushed such growth toward more denser architectures, that is, mor...
Pavan Balaji, Darius Buntinas, David Goodell, Will...
DATE
2010
IEEE
122views Hardware» more  DATE 2010»
13 years 12 months ago
Optimal regulation of traffic flows in networks-on-chip
We have proposed (, )-based flow regulation to reduce delay and backlog bounds in SoC architectures, where bounds the traffic burstiness and the traffic rate. The regulation is co...
Fahimeh Jafari, Zhonghai Lu, Axel Jantsch, Mohamma...
LPNMR
2009
Springer
14 years 2 months ago
Application of ASP for Automatic Synthesis of Flexible Multiprocessor Systems from Parallel Programs
Configurable on chip multiprocessor systems combine advantages of task-level parallelism and the flexibility of field-programmable devices to customize architectures for paralle...
Harold Ishebabi, Philipp Mahr, Christophe Bobda, M...
ASPDAC
2005
ACM
100views Hardware» more  ASPDAC 2005»
13 years 9 months ago
Microarchitecture evaluation with floorplanning and interconnect pipelining
— As microprocessor technology continues to scale into the nanometer regime, recent studies show that interconnect delay will be a limiting factor for performance, and multiple c...
Ashok Jagannathan, Hannah Honghua Yang, Kris Konig...