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CODES
2006
IEEE
14 years 1 months ago
Generic netlist representation for system and PE level design exploration
Designer productivity and design predictability are vital factors for successful embedded system design. Shrinking time-to-market and increasing complexity of these systems requir...
Bita Gorjiara, Mehrdad Reshadi, Pramod Chandraiah,...
ERSA
2010
186views Hardware» more  ERSA 2010»
13 years 5 months ago
DAPR: Design Automation for Partially Reconfigurable FPGAs
Partial reconfiguration (PR) enhances traditional FPGA-based high-performance reconfigurable computing by providing additional benefits such as reduced area and memory requirements...
Shaon Yousuf, Ann Gordon-Ross
ERSA
2009
107views Hardware» more  ERSA 2009»
13 years 5 months ago
Towards Effective Modeling and Programming Multi-core Tiled Reconfigurable Architectures
For a generic flexible efficient array antenna receiver platform a hierarchical reconfigurable tiled architecture has been proposed. The architecture provides a flexible reconfigur...
Kenneth C. Rovers, Marcel D. van de Burgwal, Jan K...
INFOVIS
2003
IEEE
14 years 23 days ago
Exploring High-D Spaces with Multiform Matrices and Small Multiples
We introduce an approach to visual analysis of multivariate data that integrates several methods from information visualization, exploratory data analysis (EDA), and geovisualizat...
Alan M. MacEachren, Xiping Dai, Frank Hardisty, Di...
TVLSI
2008
119views more  TVLSI 2008»
13 years 7 months ago
Automatic Design of Reconfigurable Domain-Specific Flexible Cores
Reconfigurable hardware is ideal for use in Systems-on-a-Chip, as it provides both hardware-level performance and post-fabrication flexibility. However, any one architecture is ra...
Katherine Compton, Scott Hauck