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ICES
2003
Springer
93views Hardware» more  ICES 2003»
14 years 20 days ago
A Genetic Representation for Evolutionary Fault Recovery in Virtex FPGAs
Most evolutionary approaches to fault recovery in FPGAs focus on evolving alternative logic configurations as opposed to evolving the intra-cell routing. Since the majority of tra...
Jason D. Lohn, Gregory V. Larchev, Ronald F. DeMar...
EVOW
2006
Springer
13 years 11 months ago
Optimisation of Constant Matrix Multiplication Operation Hardware Using a Genetic Algorithm
Abstract. The efficient design of multiplierless implementations of constant matrix multipliers is challenged by the huge solution search spaces even for small scale problems. Prev...
Andrew Kinane, Valentin Muresan, Noel E. O'Connor
DATE
1999
IEEE
120views Hardware» more  DATE 1999»
13 years 11 months ago
Hardware Synthesis from C/C++ Models
Software programming languages, such as C/C++, have been used as means for specifying hardware for quite a while. Different design methodologies have exploited the advantages of f...
Giovanni De Micheli
AHS
2006
IEEE
113views Hardware» more  AHS 2006»
13 years 11 months ago
A Honeycomb Development Architecture for Robust Fault-Tolerant Design
A new hardware developmental model that shows strong robust transient fault-tolerant abilities and is motivated by embryonic development and a honeycomb structure is presented. Ca...
Andy M. Tyrrell, Hong Sun
ITC
1996
IEEE
96views Hardware» more  ITC 1996»
13 years 11 months ago
A Roadmap for Boundary-Scan Test Reuse
This paper proposes a Layered Model for boundaryscan testing to help identify opportunities for standardization. Serial Vector Format [1] and an accompanying Application Programmi...
D. Eugene Wedge, Tom Conner