104 search results - page 3 / 21 » Globally Asynchronous Locally Synchronous FPGA Architectures |
ICCD
2000
IEEE
14 years 4 months ago
2000
IEEE
We present a local clocking mechanism based on a tunable delay line which calibrates itself from a low frequency global clock. After initial tuning, the local clock remains calibr...
ISVLSI
2006
IEEE
14 years 1 months ago
2006
IEEE
This paper investigates the performance and power dissipation of Globally Asynchronous Locally Synchronous (GALS) multi-processor systems. We show that communication loops are a s...
ASYNC
2003
IEEE
14 years 20 days ago
2003
IEEE
The lack of proven mechanisms for transferring data between multiple synchronous islands has been a major impediment for applying globally asynchronous locally synchronous (GALS) ...
ISLPED
2003
ACM
14 years 19 days ago
2003
ACM
Ever shrinking device sizes and innovative micro-architectural and circuit design techniques have made it possible to have multi-million transistor systems running at multi-gigahe...
ASPDAC
2009
ACM
14 years 1 months ago
2009
ACM
— This is the first implementation of an FPGA based on autonomous fine-grain power-gating. To cut the power consumption of clock network and detect the activity of the cell e...