104 search results - page 5 / 21 » Globally Asynchronous Locally Synchronous FPGA Architectures |
ASPDAC
2011
ACM
12 years 11 months ago
2011
ACM
—This paper presents an asynchronous FPGA that combines four-phase dual-rail encoding and LEDR (Level-Encoded Dual-Rail) encoding. Four-phase dual-rail encoding is used for small...
EMSOFT
2005
Springer
14 years 27 days ago
2005
Springer
We consider the problem of synthesizing correct-by-construction globally asynchronous, locally synchronous (GALS) implementations from modular synchronous specifications. This in...
VLSISP
2008
13 years 7 months ago
2008
Abstract-- This paper presents the architecture of an Asynchronous Array of simple Processors (AsAP), and evaluates its key architectural features as well as its performance and en...
FPGA
2008
ACM
13 years 9 months ago
2008
ACM
To improve FPGA performance for arithmetic circuits, this paper proposes a new architecture for FPGA logic cells that includes a 6:2 compressor. The new cell features additional f...
ASYNC
2002
IEEE
14 years 10 days ago
2002
IEEE
Reliable, low-latency channel communication between independent clock domains may be achieved using a combination of clock pausing techniques, self-calibrating delay lines and an ...