Sciweavers

104 search results - page 6 / 21
» Globally Asynchronous Locally Synchronous FPGA Architectures
Sort
View
ICCAD
2006
IEEE
111views Hardware» more  ICCAD 2006»
14 years 4 months ago
Mapping arbitrary logic functions into synchronous embedded memories for area reduction on FPGAs
This work describes a new mapping technique, RAM-MAP, that identifies parts of circuits that can be efficiently mapped into the synchronous embedded memories found on field prog...
Gordon R. Chiu, Deshanand P. Singh, Valavan Manoha...
ISLPED
2005
ACM
147views Hardware» more  ISLPED 2005»
14 years 28 days ago
System level power and performance modeling of GALS point-to-point communication interfaces
Due to difficulties in distributing a single global clock signal over increasingly large chip areas, a globally asynchronous, locally synchronous design is considered a promising ...
Koushik Niyogi, Diana Marculescu
DCOSS
2011
Springer
12 years 7 months ago
Distributed local broadcasting algorithms in the physical interference model
—Given a set of sensor nodes V where each node wants to broadcast a message to all its neighbors that are within a certain broadcasting range, the local broadcasting problem is t...
Dongxiao Yu, Yuexuan Wang, Qiang-Sheng Hua, Franci...
ISLPED
2004
ACM
124views Hardware» more  ISLPED 2004»
14 years 24 days ago
Application adaptive energy efficient clustered architectures
As clock frequency and die area increase, achieving energy efficiency, while distributing a low skew, global clock signal becomes increasingly difficult. Challenges imposed by dee...
Diana Marculescu
TVLSI
2010
13 years 2 months ago
A Low-Area Multi-Link Interconnect Architecture for GALS Chip Multiprocessors
A new inter-processor communication architecture for chip multiprocessors is proposed which has a low area cost, flexible routing capability, and supports globally asynchronous loc...
Zhiyi Yu, Bevan M. Baas