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INFOCOM
2009
IEEE
14 years 3 months ago
Synchronized CSMA Contention: Model, Implementation and Evaluation
— A class of CSMA protocols used in a broad range of wireless applications uses synchronized contention where nodes periodically contend at intervals of fixed duration. While se...
Jing Shi, Ehsan Aryafar, Theodoros Salonidis, Edwa...
ISORC
2009
IEEE
14 years 3 months ago
On the Semantics of UML/MARTE Clock Constraints
The UML goal of being a general-purpose modeling language discards the possibility to adopt too precise and strict a semantics. Users are to refine or define the semantics in th...
Frédéric Mallet, Charles André...
DAC
1994
ACM
14 years 24 days ago
Clock Grouping: A Low Cost DFT Methodology for Delay Testing
A low overhead DFT technique, called clock-grouping, for delay testing of sequential synchronous circuits is presented. The proposed technique increases robust path delay fault co...
Wen-Chang Fang, Sandeep K. Gupta
TCAD
2002
146views more  TCAD 2002»
13 years 8 months ago
Static scheduling of multidomain circuits for fast functional verification
With the advent of system-on-a-chip design, many application specific integrated circuits (ASICs) now require multiple design clocks that operate asynchronously to each other. This...
Murali Kudlugi, Russell Tessier
DATE
2006
IEEE
104views Hardware» more  DATE 2006»
14 years 2 months ago
Integrated placement and skew optimization for rotary clocking
—The clock distribution network is a key component of any synchronous VLSI design. High power dissipation and pressure volume temperature-induced variations in clock skew have st...
Ganesh Venkataraman, Jiang Hu, Frank Liu, Cliff C....