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ICCD
2005
IEEE
121views Hardware» more  ICCD 2005»
14 years 5 months ago
Asynchronous IC Interconnect Network Design and Implementation Using a Standard ASIC Flow
The implementation of interconnect is becoming a significant challenge in modern IC design. Both synchronous and asynchronous strategies have been suggested to manage this problem...
Bradley R. Quinton, Mark R. Greenstreet, Steven J....
ASYNC
2002
IEEE
124views Hardware» more  ASYNC 2002»
14 years 1 months ago
Synchronous Interlocked Pipelines
In a circuit environment that is becoming increasingly sensitive to dynamic power dissipation and noise, and where cycle time available for control decisions continues to decrease...
Hans M. Jacobson, Prabhakar Kudva, Pradip Bose, Pe...
ISPD
2004
ACM
146views Hardware» more  ISPD 2004»
14 years 2 months ago
Power-aware clock tree planning
Modern processors and SoCs require the adoption of poweroriented design styles, due to the implications that power consumption may have on reliability, cost and manufacturability ...
Monica Donno, Enrico Macii, Luca Mazzoni
ICMCS
2009
IEEE
124views Multimedia» more  ICMCS 2009»
13 years 6 months ago
Swarm synchronization for multi-recipient multimedia streaming
IP networks allow constructing versatile device configurations for multimedia streaming. However, the stochastic nature of the packet-switched data transmission may complicate IP-...
Mika Rautiainen, Hannu Aska, Timo Ojala, Matti Hos...
DATE
2000
IEEE
110views Hardware» more  DATE 2000»
14 years 1 months ago
Stochastic Modeling and Performance Evaluation for Digital Clock and Data Recovery Circuits
Clock and data recovery circuits are essential components in communication systems. They directly influence the bit-error-rate performance of communication links. It is desirable...
Alper Demir, Peter Feldmann