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DATE
2006
IEEE
104views Hardware» more  DATE 2006»
14 years 4 months ago
Contrasting a NoC and a traditional interconnect fabric with layout awareness
Increasing miniaturization is posing multiple challenges to electronic designers. In the context of Multi-Processor System-onChips (MPSoCs), we focus on the problem of implementin...
Federico Angiolini, Paolo Meloni, Salvatore Carta,...
ISPD
1998
ACM
128views Hardware» more  ISPD 1998»
14 years 2 months ago
Topology constrained rectilinear block packing for layout reuse
In this paper, we formulate the problem of topology constrained rectilinear block packing in layout reuse. A speci c class of rectilinear shaped blocks, ordered convex rectilinear...
Maggie Zhiwei Kang, Wayne Wei-Ming Dai
ICCAD
1997
IEEE
91views Hardware» more  ICCAD 1997»
14 years 2 months ago
Interconnect layout optimization under higher-order RLC model
In this paper, we study the interconnect layout optimization problem under a higher-order RLC model to optimize not just delay, but also waveform for RLC circuits with non-monoton...
Jason Cong, Cheng-Kok Koh
SODA
2010
ACM
278views Algorithms» more  SODA 2010»
14 years 7 months ago
The edge disjoint paths problem in Eulerian graphs and $4$-edge-connected graphs
We consider the following well-known problem, which is called the edge-disjoint paths problem. Input: A graph G with n vertices and m edges, k pairs of vertices (s1, t1), (s2, t2)...
Ken-ichi Kawarabayashi, Yusuke Kobayashi
ORL
2007
82views more  ORL 2007»
13 years 9 months ago
The path partition problem and related problems in bipartite graphs
We prove that it is NP-complete to decide whether a bipartite graph of maximum degree three on nk vertices can be partitioned into n paths of length k. Finally, we propose some ap...
Jérôme Monnot, Sophie Toulouse