227 search results - page 34 / 46 » Graph Rewriting for Hardware Dependent Program Optimizations |
IESS
2007
Springer
14 years 1 months ago
2007
Springer
Abstract This paper presents an embedded system design toolchain for automatic generation of parallel code runnable on symmetric multiprocessor systems from an initial sequential s...
CC
2007
Springer
14 years 1 months ago
2007
Springer
To achieve high resource utilization for multi-issue Digital Signal Processors (DSPs), production compilers commonly include variants of the iterative modulo scheduling algorithm. ...
HPCA
1998
IEEE
13 years 11 months ago
1998
IEEE
The performance of a concurrent multithreaded architectural model, called superthreading 15 , is studied in this paper. It tries to integrate optimizing compilation techniques and...
TVLSI
2010
13 years 2 months ago
2010
The gap between VLSI technology and fabrication technology leads to strong refractive effects in lithography. Consequently, it is a huge challenge to reliably print layout features...
ICS
1999
Tsinghua U.
13 years 11 months ago
1999
Tsinghua U.
Hydra is a chip multiprocessor (CMP) with integrated support for thread-level speculation. Thread-level speculation provides a way to parallelize sequential programs without the n...