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CODES
2005
IEEE
14 years 28 days ago
Designing real-time H.264 decoders with dataflow architectures
High performance microprocessors are designed with generalpurpose applications in mind. When it comes to embedded applications, these architectures typically perform controlintens...
Youngsoo Kim, Suleyman Sair
ISPASS
2006
IEEE
14 years 1 months ago
Critical path analysis of the TRIPS architecture
Fast, accurate, and effective performance analysis is essential for the design of modern processor architectures and improving application performance. Recent trends toward highly...
Ramadass Nagarajan, Xia Chen, Robert G. McDonald, ...
CODES
2005
IEEE
14 years 28 days ago
DVS for buffer-constrained architectures with predictable QoS-energy tradeoffs
We present a new scheme for dynamic voltage and frequency scaling (DVS) for processing multimedia streams on architectures with restricted buffer sizes. The main advantage of our ...
Alexander Maxiaguine, Samarjit Chakraborty, Lothar...
HASE
1997
IEEE
13 years 11 months ago
ReSoFT: A Reusable Testbed for Development and Evaluation of Software Fault-Tolerant Systems
The Reusable Software Fault Tolerance Testbed ReSoFT was developed to facilitate the development and evaluation of high-assurance systems that require tolerance of both hardware...
Kam S. Tso, Eltefaat Shokri, Roger J. Dziegiel Jr.
DATE
2006
IEEE
125views Hardware» more  DATE 2006»
14 years 1 months ago
Formal performance analysis and simulation of UML/SysML models for ESL design
UML2 and SysML try to adopt techniques known from software development to systems engineering. However, the focus has been put on modeling aspects until now and quantitative perfo...
Alexander Viehl, Timo Schönwald, Oliver Bring...