Sciweavers

19 search results - page 3 / 4
» Guaranteeing Hits to Improve the Efficiency of a Small Instr...
Sort
View
IWSOC
2003
IEEE
104views Hardware» more  IWSOC 2003»
14 years 1 months ago
Incorporating Pattern Prediction Technique for Energy Efficient Filter Cache Design
: - A filter cache is proposed at a higher level than the L1 (main) cache in the memory hierarchy and is much smaller. The typical size of filter cache is of the order of 512 Bytes...
Kugan Vivekanandarajah, Thambipillai Srikanthan, S...
MICRO
2002
IEEE
117views Hardware» more  MICRO 2002»
13 years 8 months ago
Drowsy instruction caches: leakage power reduction using dynamic voltage scaling and cache sub-bank prediction
On-chip caches represent a sizeable fraction of the total power consumption of microprocessors. Although large caches can significantly improve performance, they have the potentia...
Nam Sung Kim, Krisztián Flautner, David Bla...
HPCA
2009
IEEE
14 years 9 months ago
Criticality-based optimizations for efficient load processing
Some instructions have more impact on processor performance than others. Identification of these critical instructions can be used to modify and improve instruction processing. Pr...
Samantika Subramaniam, Anne Bracy, Hong Wang 0003,...
GECCO
2009
Springer
192views Optimization» more  GECCO 2009»
13 years 6 months ago
Improving SMT performance: an application of genetic algorithms to configure resizable caches
Simultaneous Multithreading (SMT) is a technology aimed at improving the throughput of the processor core by applying Instruction Level Parallelism (ILP) and Thread Level Parallel...
Josefa Díaz, José Ignacio Hidalgo, F...
WWW
2007
ACM
14 years 9 months ago
Improving the Performance of Online Auctions Through Server-side Activity-based Caching
Online auction sites have very specific workloads and user behavior characteristics. Previous studies on workload characterization conducted by the authors showed that i) bidding a...
Daniel A. Menascé, Vasudeva Akula