27 search results - page 1 / 6 » Guiding Circuit Level Fault-Tolerance Design with Statistica... |
DATE
2008
IEEE
14 years 5 months ago
2008
IEEE
In the last decade, the focus of fault-tolerance methods has tended towards circuit level modifications, such as transistor resizing, and away from expensive system level redunda...
IOLTS
2003
IEEE
14 years 4 months ago
2003
IEEE
Fault tolerant design is a technique emerging in Integrated Circuits (IC’s) to deal with the increasing error susceptibility (Soft Errors, or Single Event Upsets, SEU) caused by...
DATE
2005
IEEE
14 years 4 months ago
2005
IEEE
- The problem of determining lower bounds for the energy cost of a given nanoscale design is addressed via a complexity theory-based approach. This paper provides a theoretical fra...
ICAC
2005
IEEE
14 years 4 months ago
2005
IEEE
This paper proposes autonomic or organic computing principles to be applied to hardware design methods for future SoC solutions. Incorporating self-calibration, fault tolerance or...
DAC
2008
ACM
15 years 6 min ago
2008
ACM
As integrated circuit technology plumbs ever greater depths in the scaling of feature sizes, maintaining the paradigm of deterministic Boolean computation is increasingly challeng...