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HPCA
2006
IEEE
14 years 10 months ago
Efficient instruction schedulers for SMT processors
We propose dynamic scheduler designs to improve the scheduler scalability and reduce its complexity in the SMT processors. Our first design is an adaptation of the recently propos...
Joseph J. Sharkey, Dmitry V. Ponomarev
HPCA
2003
IEEE
14 years 10 months ago
Slipstream Execution Mode for CMP-Based Multiprocessors
Scalability of applications on distributed sharedmemory (DSM) multiprocessors is limited by communication overheads. At some point, using more processors to increase parallelism y...
Khaled Z. Ibrahim, Gregory T. Byrd, Eric Rotenberg
DSN
2007
IEEE
14 years 4 months ago
Utilizing Dynamically Coupled Cores to Form a Resilient Chip Multiprocessor
Aggressive CMOS scaling will make future chip multiprocessors (CMPs) increasingly susceptible to transient faults, hard errors, manufacturing defects, and process variations. Exis...
Christopher LaFrieda, Engin Ipek, José F. M...
ANCS
2006
ACM
14 years 3 months ago
Localized asynchronous packet scheduling for buffered crossbar switches
Buffered crossbar switches are a special type of crossbar switches. In such a switch, besides normal input queues and output queues, a small buffer is associated with each crosspo...
Deng Pan, Yuanyuan Yang
CONEXT
2006
ACM
14 years 3 months ago
Migrating home agents towards internet-scale mobility deployments
While the IETF standardization process of the Mobile IPv6 and Network Mobility (NEMO) protocols is almost complete, their large-scale deployment is not yet possible. With these te...
Ryuji Wakikawa, Guillaume Valadon, Jun Murai