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» Hardware Accelerated Power Estimation
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102
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ISMVL
2000
IEEE
81views Hardware» more  ISMVL 2000»
15 years 7 months ago
Propagation Algorithm of Behavior Probability in Power Estimation Based on Multiple-Valued Logic
— This paper analyses the propagation operations of signal’s multiple-valued behavior while passing through the basic gates. Based on it the propagation algorithm of behavior p...
Xunwei Wu, Massoud Pedram
151
Voted
FPGA
2008
ACM
133views FPGA» more  FPGA 2008»
15 years 4 months ago
Vector processing as a soft-core CPU accelerator
The currently accepted method of accelerating applications in FPGA soft processor systems is to design a custom hardware accelerator. This paper suggests the alternative approach ...
Jason Yu, Guy Lemieux, Christopher Eagleston
111
Voted
FPL
2008
Springer
153views Hardware» more  FPL 2008»
15 years 4 months ago
FPGA acceleration of quasi-Monte Carlo in finance
Today, quasi-Monte Carlo (QMC) methods are widely used in finance to price derivative securities. The QMC approach is popular because for many types of derivatives it yields an es...
Nathan A. Woods, Tom VanCourt
ASPDAC
2006
ACM
140views Hardware» more  ASPDAC 2006»
15 years 8 months ago
A cycle accurate power estimation tool
- Power consumption is one of the major challenges in VLSI Design. Power constrained designs need tools to accurately predict the power consumption and provide feedback to designer...
Rajat Chaudhry, Daniel L. Stasiak, Stephen D. Posl...
97
Voted
DAC
2008
ACM
16 years 3 months ago
DVFS in loop accelerators using BLADES
Hardware accelerators are common in embedded systems that have high performance requirements but must still operate within stringent energy constraints. To facilitate short time-t...
Ganesh S. Dasika, Shidhartha Das, Kevin Fan, Scott...