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» Hardware Acceleration of HMMER on FPGAs
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FPL
2010
Springer
148views Hardware» more  FPL 2010»
13 years 5 months ago
FEM: A Step Towards a Common Memory Layout for FPGA Based Accelerators
FPGA devices are mostly utilized for customized application designs with heavily pipelined and aggressively parallel computations. However, little focus is normally given to the FP...
Muhammad Shafiq, Miquel Pericàs, Nacho Nava...
FPL
2009
Springer
162views Hardware» more  FPL 2009»
13 years 11 months ago
Efficient particle-pair filtering for acceleration of molecular dynamics simulation
The acceleration of molecular dynamics (MD) simulations using high performance reconfigurable computing (HPRC) has been much studied. Given the intense competition from multicore...
Matt Chiu, Martin C. Herbordt
ICPADS
2006
IEEE
14 years 1 months ago
Scalable Hybrid Designs for Linear Algebra on Reconfigurable Computing Systems
—Recently, high-end reconfigurable computing systems that employ Field-Programmable Gate Arrays (FPGAs) as hardware accelerators for general-purpose processors have been built. T...
Ling Zhuo, Viktor K. Prasanna
FPL
2008
Springer
207views Hardware» more  FPL 2008»
13 years 9 months ago
Bitstream compression techniques for Virtex 4 FPGAs
This paper examines the opportunity of using compression for accelerating the (re)configuration of FPGA devices, focusing on the choice of compression algorithms, and their hardwa...
Radu Stefan, Sorin Dan Cotofana
FCCM
2006
IEEE
120views VLSI» more  FCCM 2006»
14 years 1 months ago
FPGAs, GPUs and the PS2 - A Single Programming Methodology
Field programmable gate arrays (FPGAs), graphics processing units (GPUs) and Sony’s Playstation 2 vector units offer scope for hardware acceleration of applications. Implementin...
Lee W. Howes, Paul Price, Oskar Mencer, Olav Beckm...