65 search results - page 10 / 13 » Hardware Architecture for Optical Flow Estimation in Real Ti... |
FPL
2008
Springer
13 years 8 months ago
2008
Springer
This paper considers the implementation of an annealing technique for dynamic power reduction in FPGAs. The proposed method comprises a power-aware objective function for placemen...
FPL
2007
Springer
14 years 26 days ago
2007
Springer
In this paper, we propose a first step towards a time predictable computer architecture for single-chip multiprocessing (CMP). CMP is the actual trend in server and desktop syste...
CVPR
2010
IEEE
14 years 3 months ago
2010
IEEE
Modeling moving and deforming objects requires capturing as much information as possible during a very short time. When using off-the-shelf hardware, this often hinders the resolu...
ASPDAC
2006
ACM
14 years 20 days ago
2006
ACM
- Early estimation of the execution time of Real-Time embedded SW is an essential task in complex, HW/SW embedded system design. Application SW execution time estimation requires t...
DAC
2006
ACM
14 years 7 months ago
2006
ACM
Field programmable dual-Vdd interconnects are effective to reduce FPGA power. Assuming uniform length interconnects, existing work has developed time slack budgeting to minimize p...