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DATE
2008
IEEE
86views Hardware» more  DATE 2008»
14 years 4 months ago
Test Scheduling for Wafer-Level Test-During-Burn-In of Core-Based SoCs
Abstract—Wafer-level test during burn-in (WLTBI) has recently emerged as a promising technique to reduce test and burn-in costs in semiconductor manufacturing. However, the testi...
Sudarshan Bahukudumbi, Krishnendu Chakrabarty, Ric...
ISQED
2007
IEEE
124views Hardware» more  ISQED 2007»
14 years 3 months ago
Multi-Dimensional Circuit and Micro-Architecture Level Optimization
This paper studies multi-dimensional optimization at both circuit and micro-architecture levels. By formulating and solving the optimization problem with conflicting design objec...
Zhenyu Qi, Matthew M. Ziegler, Stephen V. Kosonock...
EH
2005
IEEE
112views Hardware» more  EH 2005»
14 years 3 months ago
Evolving Assembly Plans for Fully Automated Design and Assembly
Evolutionary Design has demonstrated great potential to automatically generate a wide array of novel, interesting, and human-competitive designs. Few of these evolved designs, how...
John Rieffel, Jordan B. Pollack
SI3D
2003
ACM
14 years 2 months ago
Application of the two-sided depth test to CSG rendering
Shadow mapping is a technique for doing real-time shadowing. Recent work has shown that shadow mapping hardware can be used as a second depth test in addition to the z-test. In th...
Sudipto Guha, Shankar Krishnan, Kamesh Munagala, S...
DATE
2000
IEEE
65views Hardware» more  DATE 2000»
14 years 2 months ago
Test Quality and Fault Risk in Digital Filter Datapath BIST
An objective of DSP testing should be to ensure that any errors due to missed faults are infrequent compared to a circuit’s intrinsic errors, such as overflow. A method is prop...
Laurence Goodby, Alex Orailoglu