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ASPDAC
2007
ACM
98views Hardware» more  ASPDAC 2007»
14 years 1 months ago
Fast Analytic Placement using Minimum Cost Flow
Many current integrated circuits designs, such as those released for the ISPD2005[14] placement contest, are extremely large and can contain a great deal of white space. These new...
Ameya R. Agnihotri, Patrick H. Madden
ASPDAC
2007
ACM
121views Hardware» more  ASPDAC 2007»
14 years 1 months ago
Approximation Algorithm for Process Mapping on Network Processor Architectures
The high performance requirements of networking applications has led to the advent of programmable network processor (NP) architectures that incorporate symmetric multiprocessing, ...
Christopher Ostler, Karam S. Chatha, Goran Konjevo...
ASPDAC
2004
ACM
113views Hardware» more  ASPDAC 2004»
14 years 1 months ago
Area-minimal algorithm for LUT-based FPGA technology mapping with duplication-free restriction
- Minimum area is one of the important objectives in technology mapping for lookup table-based FPGAs. It has been proven that the problem is NP-complete. This paper presents a poly...
Chi-Chou Kao, Yen-Tai Lai
ASPDAC
2004
ACM
85views Hardware» more  ASPDAC 2004»
14 years 1 months ago
Multi-level placement with circuit schema based clustering in analog IC layouts
This paper aims at developing an automated device-level placement for analog circuit design which achieves comparable quality to manual designs by experts. It extracts a set of cl...
Takashi Nojima, Xiaoke Zhu, Yasuhiro Takashima, Sh...
DATE
2004
IEEE
103views Hardware» more  DATE 2004»
14 years 29 days ago
A Novel Implementation of Tile-Based Address Mapping
Tile-based data layout has been applied to achieve various objectives such as minimizing cache conflicts and memory row switching activity. In some applications of tilebased mappi...
Sambuddhi Hettiaratchi, Peter Y. K. Cheung