Sciweavers

98 search results - page 7 / 20
» Hardware Partitioning Software for Dynamically Reconfigurabl...
Sort
View
DATE
2006
IEEE
195views Hardware» more  DATE 2006»
14 years 1 months ago
Application specific instruction processor based implementation of a GNSS receiver on an FPGA
In this paper the concept of a reconfigurable hardware macro to be used as a generic building block in lowpower, low-cost SoC for multioperable GNSS positioning is described, feat...
Götz Kappen, Tobias G. Noll
FPL
2006
Springer
91views Hardware» more  FPL 2006»
13 years 11 months ago
Reconfigurable Systems Enabled by a Network-on-Chip
A modern SoC design comprises dozens of dedicated IP cores for specialized tasks and processors for generalpurpose tasks. Flexibility is the key feature of processors, since it is...
Leandro Möller, Ismael Grehs, Ney Calazans, F...
CC
2008
Springer
240views System Software» more  CC 2008»
13 years 9 months ago
Hardware JIT Compilation for Off-the-Shelf Dynamically Reconfigurable FPGAs
JIT compilation is a model of execution which translates at run time critical parts of the program to a low level representation. Typically a JIT compiler produces machine code fro...
Etienne Bergeron, Marc Feeley, Jean-Pierre David
VLSID
2002
IEEE
126views VLSI» more  VLSID 2002»
14 years 7 months ago
A Hardware/Software Reconfigurable Architecture for Adaptive Wireless Image Communication
With the projected significant growth in mobile internet and multimedia services, there is a strong demand for nextgeneration appliances capable of wireless image communication. O...
Debashis Panigrahi, Clark N. Taylor, Sujit Dey
ICCD
1999
IEEE
130views Hardware» more  ICCD 1999»
13 years 11 months ago
Preference-Driven Hierarchical Hardware/Software Partitioning
In this paper, we present a hierarchical evolutionary approach to hardware/software partitioning for real-time embedded systems. In contrast to most of previous approaches, we app...
Gang Quan, Xiaobo Hu, Garrison W. Greenwood