398 search results - page 11 / 80 » Hardware Reuse at the Behavioral Level |
FPL
2007
Springer
14 years 2 months ago
2007
Springer
This paper describes an execution cache that uses process migration between hardware and software contexts by way of run-time reconfiguration (RTR) of Field Programmable Gate Arr...
CODES
2006
IEEE
14 years 2 months ago
2006
IEEE
The memory subsystem of a complex multiprocessor systemson-chip (MPSoC) is an important contributor to the chip power consumption. The selection of memory architecture, as well as...
IADIS
2004
13 years 9 months ago
2004
With rapid development of the Internet, e-learning system has become more and more popular. Currently, to solve the issue of sharing and reusing of teaching materials in different...
IJHPCA
2006
13 years 8 months ago
2006
In this paper, we propose a hardware performance monitor that provides support not only for measuring cache misses and the addresses associated with them, but also for determining...
DT
2010
13 years 8 months ago
2010
specified at levels of abstraction higher than the Register Transfer Level (RTL) in hardware description. The essential feature of a behavioral description is that, the designer on...