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» Hardware Reuse at the Behavioral Level
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ATS
1998
IEEE
106views Hardware» more  ATS 1998»
14 years 21 days ago
A Test Pattern Generation Algorithm Exploiting Behavioral Information
This paper aims at broadening the scope of hierarchical ATPG to the behavioral-level The main problem of using behavioral information for ATPG is the mismatch of timing models bet...
Silvia Chiusano, Fulvio Corno, Paolo Prinetto
CASES
2005
ACM
13 years 10 months ago
Anomalous path detection with hardware support
Embedded systems are being deployed as a part of critical infrastructures and are vulnerable to malicious attacks due to internet accessibility. Intrusion detection systems have b...
Tao Zhang, Xiaotong Zhuang, Santosh Pande, Wenke L...
ISVLSI
2006
IEEE
126views VLSI» more  ISVLSI 2006»
14 years 2 months ago
QUKU: A Two-Level Reconfigurable Architecture
FPGAs have been used for prototyping of ASICs, for low-volume ASIC replacement and for systems requiring in-field hardware upgrades. However, the potential to use dynamic reconfig...
Sunil Shukla, Neil W. Bergmann, Jürgen Becker
VLSID
1999
IEEE
139views VLSI» more  VLSID 1999»
14 years 21 days ago
Processor Modeling for Hardware Software Codesign
In hardware - software codesign paradigm often a performance estimation of the system is needed for hardware - software partitioning. The tremendous growth of application specific...
V. Rajesh, Rajat Moona
ASPDAC
2004
ACM
106views Hardware» more  ASPDAC 2004»
14 years 1 months ago
A novel memory size model for variable-mapping in system level design
— It is predicted that 70% of the chip area will be occupied by memories in future system-onchips. The minimization of on-chip memory hence becomes increasingly important for cos...
Lukai Cai, Haobo Yu, Daniel Gajski